December 13 – 14, 2022
December 12 – Member Only Day + FUTUREWATCH
December 15 – TUTORIAL DAY
San jose, ca
You Won’t Want to Miss RISC-V’s Global Summit This December
Each day, thousands of engineers around the world collaborate and contribute to advance the most prolific open, license and royalty-free computing architecture. They share technical investment and help shape the architecture’s strategic future so everyone may create more rapidly, enjoy unprecedented design freedom, and substantially reduce the cost of innovation. Anyone, anywhere can benefit from the open intellectual property contributed by RISC-V.
This December, the RISC-V community – including the technical, industry, domain and special interest groups who define the architecture’s specifications – will be in San Jose, California for four days of technology breakthroughs, industry milestones, tutorials, and relationship building.
The community-curated content you’ll experience is unparalleled.
Automotive. High-performance Computing. Data Centers. ML and AI. Security. Software Stacks. Development Tools. Systems on a Chip. It’s all here. And it’s all new.
Break new ground. Define the future. Grow your network. Build your expertise. Meet your heroes. It’s all during RISC-V Summit North America, this December in San Jose.
Featured Keynote Speakers
Calista Redmond is the CEO of RISC-V International with a mission to expand and engage RISC-V stakeholders, compel industry adoption, and increase visibility and opportunity for RISC-V within and beyond RISC-V International. Prior to RISC-V International, Calista held a variety of roles at IBM, including Vice President of IBM Z Ecosystem where she led strategic relationships across software vendors, system integrators, business partners, developer communities, and broader engagement across the industry. Focus areas included execution of commercialization strategies, technical and business support for partners, and matchmaker to opportunities across the IBM Z and LinuxOne community. Calista’s background includes building and leading strategic business models within IBM’s Systems Group through open source initiatives including OpenPOWER, OpenDaylight, and Open Mainframe Project. For OpenPOWER, Calista was a leader in drafting the strategy, cultivating the foundation of partners, and nurturing strategic relationships to grow the org from zero to 300+ members. While at IBM, she also drove numerous acquisition and divestiture missions, and several strategic alliances. Prior to IBM, she was an entrepreneur in four successful start-ups in the IT industry. Calista holds degrees from the University of Michigan and Northwestern University.
Lip-Bu Tan Chairman, Walden International Founding Managing Partner, Celesta Capital and Walden Catalyst Ventures Executive Chairman, Cadence Design Systems, Inc.
Lip-Bu Tan is Founder and Chairman of Walden International (“WI”), a leading venture capital firm managing cumulative capital commitments of greater than $4 billion; and Founding Managing Partner of Celesta Capital and Walden Catalyst Ventures, a venture capital firm focused on investing in core technology companies. He formerly served as Chief Executive Officer of Cadence Design Systems, Inc., and now serves as Executive Chairman and has been a member of the Cadence Board of Directors since 2004. He currently serves on the Board of Schneider Electric SE (SU: FP), Intel Corporation (NASDAQ: INTC), and Credo Semiconductor (NASDAQ:CRDO).
Lip-Bu focuses on semiconductor/components, cloud/edge infrastructure, data management and security, and AI/machine learning.
Lip-Bu received his B.S. from Nanyang University in Singapore, his M.S. in Nuclear Engineering from the
Massachusetts Institute of Technology, and his MBA from the University of San Francisco. He also received his honorary degree for Doctor of Humane Letters from the University of San Francisco. Lip-Bu currently serves on Carnegie Mellon University’s (CMU) Board of Trustees and the School of Engineering Dean’s Council, and on Fuller Theological Seminary’s Board of Trustees. He’s a member of the University of California Berkeley’s College of Engineering Advisory Board and their Computing, Data Science, and Society Advisory Board, a Global Advisory Board Member of METI Japan, and a member of The Business Council and Committee 100.
Simon Davidmann has been working on simulators and EDA products since 1978. He is founder and CEO of Imperas and initiator of Open Virtual Platforms (www.OVPworld.org) – the place for Fast Processor Models. Prior to founding Imperas, Simon was a VP in Synopsys following its successful acquisition of Co-Design Automation, the developer of SystemVerilog. Prior to founding Co-Design Automation, Simon was an executive or European GM with 5 US-based EDA startups including Chronologic Simulation, which pioneered the compiled code simulator VCS, and Ambit, which was acquired by Cadence for $280M. Simon was one of the original developers of the HILO logic simulation system, and co-authored the definitive book on SystemVerilog.
Balaji Baktha is the founder, chairman and CEO of Ventana Micro Systems. He is an experienced semiconductor executive and serial technology entrepreneur and investor. Previously, Balaji founded Veloce Technologies, the world’s first 64-bit ARM based high performance processor. Prior to that he was President and CEO at mobile image signal processor SOC company Insilica. Previously Balaji held leadership roles at Marvell Semiconductor, Adaptec (now Microsemi), and SCM Micro Systems.
Dr. Black has over 30 years of industry experience. Before joining Codasip, he has been President and CEO at Imagination Technologies and previously CEO at Rambus, MobiWire, UPEK, and Wavecom. He holds a BS and MS in Engineering and a Ph.D. in Materials science from Cornell University. A consistent thread of his career has been processors including PowerPC at IBM, network processors at Freescale, security processors at Rambus, and GPUs at Imagination.
Bruce Weyer is a semiconductor industry veteran with over 35 years of experience. He joined Microchip Technology in 2014 and currently leads the company’s FPGA business unit, where he is responsible for the unit’s operational execution, strategy and growth. Bruce has held leadership roles of increasing prominence at various semiconductor companies. Prior to Microchip, he was the senior vice president of Strategic and Corporate Marketing at Cypress Semiconductor and has also served as the corporate officer responsible for global marketing at both Amalfi Semiconductor and OmniVision Technologies. He holds a BSEE from Purdue University and a Master’s in Business Administration from Santa Clara University.
Krste Asanović is a Professor in the EECS Department at the University of California, Berkeley. He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005. He returned to join the faculty at Berkeley in 2007, where he co-founded the Berkeley Parallel Computing Laboratory (“Par Lab”), and led the ASPIRE Lab, and co-led the ADEPT Lab. His main research areas are computer architecture, VLSI design, parallel programming and operating system design. He is currently Co-Director of the new Berkeley SLICE lab, which is improving specialized computing ecosystems, and is also an Associate Director at the Berkeley Wireless Research Center. He leads the free RISC-V ISA project at Berkeley, is Chairman of the RISC-V Foundation, and is Chief Architect and co-founder of SiFive Inc. He is an ACM Fellow and an IEEE Fellow.
Pete Fiacco Member HPSC Leadership Team, JPL Consultant, Managing Partner, Executive Technology Consulting
Pete Fiacco is an award-winning CTO, Founder and technology leader. A recognized semiconductor industry expert on SOCs (System-on-Chip) that focus on Storage, CPU, GPU, FPGA and networking technologies. Pete built and led teams that have delivered thousands of key industry innovations and billions of dollars in product revenue and market valuations. He is a recognized expert witness at the state and federal level, a Dean’s Advisor, Expert-in-Residence (EiR), research participant and portfolio executive with NASA/JPL, UC Irvine, UC Berkeley, CSUF, CSUP and Start-up/Technology Incubators OCTANe, UCI Applied Innovations and EvoNexus. Pete earned multiple degrees in engineering and computer engineering and holds 14 patents.
Pete is currently Managing Partner, Executive Technology Consulting, an independent technical consulting firm specializing in SOCs and other High-Performance Computing (HPC) Technologies. He is under contract with JPL/NASA and a member of the HPSC (High Performance Space Computer) Leadership Team.
Dr. Charlie Su, Co-founder, President and CTO of Andes Technology, has overseen engineering and marketing since the company started in 2005. Under his leadership, Andes developed processor IP solutions based on its own ISA before joining the RISC-V Foundation as a founding member in 2016. Charlie spent 12 years in Silicon Valley with various technical and management positions. Prior to Andes, he led the CPU and DSP IP development at Faraday as Chief Architect. He obtained his Ph.D. in Computer Science at University of Illinois Urbana-Champaign, M.S. in Computer Science at National Tsing-Hua University, and B.S. in Electrical Engineering at National Taiwan University.
Patrick is Chairman, President, and CEO of SiFive. As a business leader and technologist, he has led SiFive’s accelerated expansion into high performance RISC-V computing platforms. Previously, he was Senior Vice President & General Manager at Qualcomm, where he led their successful diversification into the automotive industry and was recognized in Motor Trend’s 2018 Power List as one of the automotive industry’s top innovators. Patrick has more than 30 years of operating experience in executive and engineering roles in the technology and semiconductor industries, including Senior Vice President & General Manager of Xilinx, Senior Vice President of CSR Technology, and CEO of eASIC Corporation (acquired by Intel). Patrick has served on the board of directors of numerous public and private technology companies throughout his career.
Jing Yang received her Ph.D. and Master in EECS from UC Berkeley. She is currently the VP of Ecosystem of T-head at Alibaba and sales head. Her current job focuses on building ecosystem for RISC-V, executing strategy across cloud and IoT. She is taking the lead to establish business relationship with the key industrial leaders and customers, plan roadmap for technology, drive product positioning and cooperate with ecosystem partners in an open environment.
Zvonimir Bandic VP Engineering, Cadence
Shreyas is currently Vice President of Compute at Imagination, responsible for Imagination’s CPU, AI and Heterogeneous compute products and solutions. He has spent 20 years in the technology industry both in start-ups and in large corporations in various roles. He started his journey in the UK designing CPUs at Arm before moving to a start-up, Apical, where he was a core catalyst in its successful journey from an early start-up stage through to acquisition. At Apical his roles included Head of Engineering and Head of Strategic Marketing. Apical was acquired by Arm for $350m and its technology has found its way into 2billion+ devices. After spending a further few years at Arm looking after product management, he joined Imagination in 2019 to work on business development and then moved into a product leadership and strategy role. Shreyas holds an MBA from Cambridge Judge Business School, Masters in Analogue and Digital IC Design from Imperial College London, graduating top of his class with distinction. Shreyas is also the recipient of Bhamashah award (India) with a double gold medal for his B.Eng. in Electronics and Communications.
Lars Bergstrom is a Director of Engineering at Google on the Android team, working on their platform programming languages, including Java, C/C++, and Rust and the supporting tools and libraries. He also serves as Google’s Corporate Director to the Rust Foundation. Before Google, he was at Mozilla Research, initially contributing to the Servo browser project and directing the integration of Rust into Firefox and the partner ecosystem. Later, he led Mozilla’s AR and VR work, shipping software and building OEM relationships on many different devices.
All sessions will be held in Pacific Standard Time (PST), UTC-8.
|Monday, December 12||9:00 AM – 5:00 PM | RISC-V Member Day*|
9:00 AM – 5:00 PM | RISC-V FutureWatch**
**For Media, Analysts and Invited Guests
|Tuesday, December 13||9:00 AM – 6:30 PM | Keynotes, Expo Hall, Sessions, |
and Welcome Reception
|Wednesday, December 14||9:00 AM – 5:00 PM | Keynotes, Expo Hall, and Sessions|
|Thursday, December 15||9:00 AM – 3:00 PM | Tutorial Day|